EW Receiver Technology
Channeliser Design Suite
Channeliser Design Suite is a powerful design tool that allows users to develop, model and synthesize a wide range of channeliser configurations, using Rheinmetall Electronics UK’s market-leading ChannelCore Flex™ Channeliser IP. Cores can be configured with a range of build-time parameters. Users can explore the trade-space quickly and easily, considering Features vs. Resource Utilisation vs. Cos. The tool provides a full bit-true model allowing RF behavior to be analysed in detail. The resultant secure cores are synthesizable via native integration with Vivado IP Integrator.
- Multiple Wideband Inputs – ChannelCore Flex™ supports up to 16 Wideband Input Channels each with multi-GHz BW capability
- Large Processing Capacity – The number of enabled channels and the channel plan can be adapted at run-time, without affecting unchanged channels
- Independent Channel Tuning – The centre frequency for each channel can be tuned with high-precision at run-time.
- Precision Time-Stamping – The core is now available precision time-stamping option (to 1ns accuracy). This provides a dynamic, compensated time-stamp with the output data for each channel.
- High Dynamic Range – The core is available with a range of options supporting spurious free dynamic range from 60 to 120 dB, which optimizes the core for FPGA resource or performance.
- Independent Channel Filter Response – Users may select any one of up to 256 programmable filters per channel. Filter orders of up to 255 are supported. Specific filter coefficients an be programmed at run-time.
ChannelCore Flex™ uses a novel architecture that implements a large number of Digital Down Converter (DDC) channels very efficiently. FPGA DSP and logic resources are utilized in proportion to the log of the number of independent DDC channels, enabling thousands of channels to be implemented in a moderately-sized FPGA.
Channels can be configured (for frequency, bandwidth, gain, filter response) at run-time, without distrupting the other operational channels. This includes the user programmable option to maintain phase coherency.
The core may be configured for a wide range of configurations. Up yp sixteen inputs can be provided, supporting either real or complex data. A wide range of FPGA devices are also supported.
The huge build-time configuration flexibility and the highly capable run-time programmability of the resultant core, provides the world’s most advanced software defined channeliser for implementation on FPGA.
Wideband RF Converters
Matched RF conveter modules in 3U VPX form-facor. A down-converter available as separate modules but designed to operate together for transceiver application.
Offering processing of an instantaneous 800 MHz band of intertest across the 0.1 – 18 GHz RF spectrum, these units are capable of operating in either the 1st or 2nd Nyquist zone (with IF at either 500 MHz or 1500 MHz). With external reference clocks these may be used for applications requiring coherency such as beam-forming receivers. Low power consumption and simple control makes these units easy to integrate.
- Frequency range of 0.1 to 18 GHz
- Instantaneous BW of 800 MHz
- Options 0.5 ot 1.5 GHz IF
- Distributed gain stages
- Built-in-test source and RSSI included
- Comprehensive reference clock options
- COMINT, ELINT and SIGINT applications including Rada ESM and Comms ESM
- ECM applications
- RF spectrum survey
- Radar applications
- Radar environment simulators
Model Based Design Tool
A suite of flexible tool, targeted towards a complex EW implementation. Supporting rapid evolution, test and evaluation of complex DSP designs and bridges the ‘valley of death’ between Modelling and Implementation.
The tool support the design structures and environments with configuration management of designs and trials. Simple to establish complex models and achieving useful run-time modelling with easy translation to HW. Software interfaces are based around COTS SW tools, OS and languages for easy integration and adoption in customer workflows based around Ubuntu OS, GIT repository, Matlab, TCL, BSH, Wy, Qt, Vivado.
The tool uses high-performance hardware in three basic configurations; Lite, Standard and Enhanced. The tools and hardware natively support high-security requirements including on-the-fly data encryption of recorded data.
- Powerful managed modelling environment with comprehensive user GUI
- Supports modelling and synthesizable components in one design structure
- Comprehensive test and simulation support with archiving of test configurations, test parameters, test stimulus and test results data
- Supports distributed GIT design repositories
- Standard target hardware with Xilinx Ultrascale devices
- Ultra-high bandwidth and deep real-time storage including on-the-fly encryption
Rheinmetall Electronics UK’s Model Based Design Tool has been developed to allow rapid development, modelling, evaluation, realization and trialing of complex DSP solutions such as EW systems.
Rapid VHDL realization from a high-level modelling environment, without resorting to significant engineering support from subject matter experts, is seen by many as a key technology enabler to allow capability advantage.
The solution is not offered as a shrink-wrapped product but as a capability that can be incorporated within your VHDL design workflow to significantly improve design evolution and product development time.
The solution has the following key attributes:
- The solution exploits open COTS hardware platforms, vendor tools and high level modelling and synthesis tool to provide the user with a flexible, extensible development platform.
- The solution provides a Graphical Design Environment (GDE) for the investigation and theoretical testing of candidate waveforms, sequences and techniques to prove their viability.
- The solution provides an environment where a field trial can be emulated to mitigate risk of solution failure and ensure readiness.
- The solution provides a diagnostics platform from which the results form a field trial can be recreated and analyzed, so that lessons can be learnt and the product implementation can be incrementally improved.